000084685 001__ 84685
000084685 005__ 20200716101447.0
000084685 0247_ $$2doi$$a10.1109/TIM.2018.2877859
000084685 0248_ $$2sideral$$a109735
000084685 037__ $$aART-2019-109735
000084685 041__ $$aeng
000084685 100__ $$0(orcid)0000-0001-8648-6248$$aGarcia-Bosque, M.$$uUniversidad de Zaragoza
000084685 245__ $$aChaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA
000084685 260__ $$c2019
000084685 5060_ $$aAccess copy available to the general public$$fUnrestricted
000084685 5203_ $$aIn this paper, a new pseudorandom number generator (PRNG) based on the logistic map has been proposed. To prevent the system to fall into short period orbits as well as increasing the randomness of the generated sequences, the proposed algorithm dynamically changes the parameters of the chaotic system. This PRNG has been implemented in a Virtex 7 field-programmable gate array (FPGA) with a 32-bit fixed point precision, using a total of 510 lookup tables (LUTs) and 120 registers. The sequences generated by the proposed algorithm have been subjected to the National Institute of Standards and Technology (NIST) randomness tests, passing all of them. By comparing the randomness with the sequences generated by a raw 32-bit logistic map, it is shown that, by using only an additional 16% of LUTs, the proposed PRNG obtains a much better performance in terms of randomness, increasing the NIST passing rate from 0.252 to 0.989. Finally, the proposed bitwise dynamical PRNG is compared with other chaos-based realizations previously proposed, showing great improvement in terms of resources and randomness.
000084685 536__ $$9info:eu-repo/grantAgreement/ES/MEC/FPU14-03523$$9info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2014-52840-R$$9info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2017-85867-R
000084685 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000084685 590__ $$a3.658$$b2019
000084685 591__ $$aINSTRUMENTS & INSTRUMENTATION$$b9 / 64 = 0.141$$c2019$$dQ1$$eT1
000084685 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b65 / 266 = 0.244$$c2019$$dQ1$$eT1
000084685 592__ $$a1.027$$b2019
000084685 593__ $$aInstrumentation$$c2019$$dQ1
000084685 593__ $$aElectrical and Electronic Engineering$$c2019$$dQ1
000084685 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion
000084685 700__ $$aPerez-Resa, A.$$uUniversidad de Zaragoza
000084685 700__ $$0(orcid)0000-0002-8236-825X$$aSanchez-Azqueta, C.$$uUniversidad de Zaragoza
000084685 700__ $$0(orcid)0000-0003-2874-6368$$aAldea, C.$$uUniversidad de Zaragoza
000084685 700__ $$0(orcid)0000-0003-0182-7723$$aCelma, S.$$uUniversidad de Zaragoza
000084685 7102_ $$12002$$2385$$aUniversidad de Zaragoza$$bDpto. Física Aplicada$$cÁrea Física Aplicada
000084685 7102_ $$15008$$2X$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cProy. investigación JBA
000084685 7102_ $$15008$$2250$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Electrónica
000084685 773__ $$g68, 1 (2019), 291-293$$pIEEE trans. instrum. meas.$$tIEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT$$x0018-9456
000084685 8564_ $$s1029916$$uhttps://zaguan.unizar.es/record/84685/files/texto_completo.pdf$$yPostprint
000084685 8564_ $$s582919$$uhttps://zaguan.unizar.es/record/84685/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint
000084685 909CO $$ooai:zaguan.unizar.es:84685$$particulos$$pdriver
000084685 951__ $$a2020-07-16-09:04:17
000084685 980__ $$aARTICLE