000085424 001__ 85424
000085424 005__ 20200716101549.0
000085424 0247_ $$2doi$$a10.1371/journal.pone.0220135
000085424 0248_ $$2sideral$$a114602
000085424 037__ $$aART-2019-114602
000085424 041__ $$aeng
000085424 100__ $$aNavarro-Torres, Agustín$$uUniversidad de Zaragoza
000085424 245__ $$aMemory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP
000085424 260__ $$c2019
000085424 5060_ $$aAccess copy available to the general public$$fUnrestricted
000085424 5203_ $$aSPEC CPU is one of the most common benchmark suites used in computer architecture research. CPU2017 has recently been released to replace CPU2006. In this paper we present a detailed evaluation of the memory hierarchy performance for both the CPU2006 and single-threaded CPU2017 benchmarks. The experiments were executed on an Intel Xeon Skylake-SP, which is the first Intel processor to implement a mostly non-inclusive last-level cache (LLC). We present a classification of the benchmarks according to their memory pressure and analyze the performance impact of different LLC sizes. We also test all the hardware prefetchers showing they improve performance in most of the benchmarks. After comprehensive experimentation, we can highlight the following conclusions: i) almost half of SPEC CPU benchmarks have very low miss ratios in the second and third level caches, even with small LLC sizes and without hardware prefetching, ii) overall, the SPEC CPU2017 benchmarks demand even less memory hierarchy resources than the SPEC CPU2006 ones, iii) hardware prefetching is very effective in reducing LLC misses for most benchmarks, even with the smallest LLC size, and iv) from the memory hierarchy standpoint the methodologies commonly used to select benchmarks or simulation points do not guarantee representative workloads.
000085424 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58-17R$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R
000085424 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000085424 590__ $$a2.74$$b2019
000085424 591__ $$aMULTIDISCIPLINARY SCIENCES$$b27 / 71 = 0.38$$c2019$$dQ2$$eT2
000085424 592__ $$a1.023$$b2019
000085424 593__ $$aMultidisciplinary$$c2019$$dQ1
000085424 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000085424 700__ $$0(orcid)0000-0003-4164-5078$$aAlastruey-Benedé, Jesús$$uUniversidad de Zaragoza
000085424 700__ $$0(orcid)0000-0002-5916-7898$$aIbáñez-Marín, Pablo$$uUniversidad de Zaragoza
000085424 700__ $$0(orcid)0000-0002-5976-1352$$aViñals-Yúfera, Víctor$$uUniversidad de Zaragoza
000085424 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000085424 773__ $$g14, 8 (2019), e0220135 [24 pp.]$$pPLoS One$$tPLoS ONE$$x1932-6203
000085424 8564_ $$s2427677$$uhttps://zaguan.unizar.es/record/85424/files/texto_completo.pdf$$yVersión publicada
000085424 8564_ $$s460760$$uhttps://zaguan.unizar.es/record/85424/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000085424 909CO $$ooai:zaguan.unizar.es:85424$$particulos$$pdriver
000085424 951__ $$a2020-07-16-09:44:29
000085424 980__ $$aARTICLE