000086215 001__ 86215 000086215 005__ 20230914083247.0 000086215 0247_ $$2doi$$a10.3390/electronics8060623 000086215 0248_ $$2sideral$$a114988 000086215 037__ $$aART-2019-114988 000086215 041__ $$aeng 000086215 100__ $$0(orcid)0000-0001-8648-6248$$aGarcia-Bosque, M.$$uUniversidad de Zaragoza 000086215 245__ $$aA 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 m CMOS Technology 000086215 260__ $$c2019 000086215 5060_ $$aAccess copy available to the general public$$fUnrestricted 000086215 5203_ $$aIn this work, a novel chaos-based stream cipher based on a skew tent map is proposed and implemented in a 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) technology. The proposed ciphering algorithm uses a linear feedback shift register that perturbs the orbits generated by the skew tent map after each iteration. This way, the randomness of the generated sequences is considerably improved. The implemented stream cipher was capable of achieving encryption speeds of 1 Gbps by using an approximate area of ~20,000 2-NAND equivalent gates, with a power consumption of 24.1 mW. To test the security of the proposed cipher, the generated keystreams were subjected to National Institute of Standards and Technology (NIST) randomness tests, proving that they were undistinguishable from truly random sequences. Finally, other security aspects such as the key sensitivity, key space size, and security against reconstruction attacks were studied, proving that the stream cipher is secure. 000086215 536__ $$9info:eu-repo/grantAgreement/ES/MEC/FPU14-03523$$9info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2017-85867-R$$9info:eu-repo/grantAgreement/ES/MINECO/TEC2014-52840 000086215 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/ 000086215 590__ $$a2.412$$b2019 000086215 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b125 / 265 = 0.472$$c2019$$dQ2$$eT2 000086215 592__ $$a0.303$$b2019 000086215 593__ $$aElectrical and Electronic Engineering$$c2019$$dQ2 000086215 593__ $$aControl and Systems Engineering$$c2019$$dQ3 000086215 593__ $$aSignal Processing$$c2019$$dQ3 000086215 593__ $$aHardware and Architecture$$c2019$$dQ3 000086215 593__ $$aComputer Networks and Communications$$c2019$$dQ3 000086215 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion 000086215 700__ $$0(orcid)0000-0001-9131-0861$$aDiez-Señorans, G.$$uUniversidad de Zaragoza 000086215 700__ $$aPérez-Resa, A.$$uUniversidad de Zaragoza 000086215 700__ $$0(orcid)0000-0002-8236-825X$$aSánchez-Azqueta, C.$$uUniversidad de Zaragoza 000086215 700__ $$0(orcid)0000-0003-2874-6368$$aAldea, C.$$uUniversidad de Zaragoza 000086215 700__ $$0(orcid)0000-0003-0182-7723$$aCelma, S.$$uUniversidad de Zaragoza 000086215 7102_ $$12002$$2385$$aUniversidad de Zaragoza$$bDpto. Física Aplicada$$cÁrea Física Aplicada 000086215 7102_ $$15008$$2X$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cProy. investigación JBA 000086215 7102_ $$15008$$2250$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Electrónica 000086215 773__ $$g8 (2019), 623 [1-10]$$pElectronics (Basel)$$tElectronics$$x2079-9292 000086215 8564_ $$s2791523$$uhttps://zaguan.unizar.es/record/86215/files/texto_completo.pdf$$yVersión publicada 000086215 8564_ $$s99173$$uhttps://zaguan.unizar.es/record/86215/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada 000086215 909CO $$ooai:zaguan.unizar.es:86215$$particulos$$pdriver 000086215 951__ $$a2023-09-13-10:50:28 000086215 980__ $$aARTICLE