000086284 001__ 86284
000086284 005__ 20200716101439.0
000086284 0247_ $$2doi$$a10.1016/j.jpdc.2018.11.005
000086284 0248_ $$2sideral$$a109699
000086284 037__ $$aART-2019-109699
000086284 041__ $$aeng
000086284 100__ $$aDíaz, J.
000086284 245__ $$aReD: A reuse detector for content selection in exclusive shared last-level caches
000086284 260__ $$c2019
000086284 5060_ $$aAccess copy available to the general public$$fUnrestricted
000086284 5203_ $$aThe reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive caches. In this paper, we propose the Reuse Detector (ReD), a new content selection mechanism for exclusive hierarchies that leverages reuse locality at the SLLC, a property that states that blocks referenced more than once are more likely to be accessed in the near future. Being placed between each L2 private cache and the SLLC, ReD prevents the insertion of blocks without reuse into the SLLC. It is designed to overcome problems affecting similar recent mechanisms (low accuracy, reduced visibility window and detector thrashing). ReD improves performance over other state-of-the-art proposals (CHAR, Reuse Cache and EAF cache). Compared with the baseline system with no content selection, it reduces the SLLC miss rate (MPI) by 10.1% and increases harmonic IPC by 9.5%.
000086284 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58-17R$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2015-65316-P$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R
000086284 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000086284 590__ $$a2.296$$b2019
000086284 592__ $$a0.525$$b2019
000086284 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b35 / 108 = 0.324$$c2019$$dQ2$$eT1
000086284 593__ $$aArtificial Intelligence$$c2019$$dQ2
000086284 593__ $$aComputer Networks and Communications$$c2019$$dQ2
000086284 593__ $$aHardware and Architecture$$c2019$$dQ2
000086284 593__ $$aSoftware$$c2019$$dQ2
000086284 593__ $$aTheoretical Computer Science$$c2019$$dQ3
000086284 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion
000086284 700__ $$aMonreal, T.
000086284 700__ $$0(orcid)0000-0002-5916-7898$$aIbáñez, P.$$uUniversidad de Zaragoza
000086284 700__ $$aLlabería, J.M.
000086284 700__ $$0(orcid)0000-0002-5976-1352$$aViñals, V.$$uUniversidad de Zaragoza
000086284 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000086284 773__ $$g125 (2019), 106-120$$pJ. parallel distrib. comput.$$tJOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING$$x0743-7315
000086284 8564_ $$s310563$$uhttps://zaguan.unizar.es/record/86284/files/texto_completo.pdf$$yPostprint
000086284 8564_ $$s25985$$uhttps://zaguan.unizar.es/record/86284/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint
000086284 909CO $$ooai:zaguan.unizar.es:86284$$particulos$$pdriver
000086284 951__ $$a2020-07-16-08:57:15
000086284 980__ $$aARTICLE