000089637 001__ 89637
000089637 005__ 20210303162449.0
000089637 0247_ $$2doi$$a10.1016/j.sysarc.2019.06.006
000089637 0248_ $$2sideral$$a113301
000089637 037__ $$aART-2019-113301
000089637 041__ $$aeng
000089637 100__ $$aRodríguez, Andrés
000089637 245__ $$aExploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs
000089637 260__ $$c2019
000089637 5060_ $$aAccess copy available to the general public$$fUnrestricted
000089637 5203_ $$aThis paper presents a framework targeted to low-cost and low-power heterogeneous MultiProcessors that exploits FPGAs and multicore CPUs, with the overarching goal of providing developers with a productive programming model and runtime support to fully use all the processing resources available. FPGA productivity is achieved using a high-level programming model based on OpenCL, the standard for cross-platform parallel heterogeneous programming. In this work, we focus on the parallel for pattern, and as part of the runtime support for this pattern, we leverage a new scheduler that strives to maximize the number of iterations per joule by dynamically and adaptively partitioning the iteration space between the multicore and the accelerator when working simultaneously. A total of 7 benchmarks are ported and optimized for a low-cost DE1 board. The results show that the heterogeneous solution can improve performance up to 2.9x and increases energy efficiency up to 2.7x compared tothe traditional approach of keeping all the CPU cores idle while the accelerator computes the workload. Our results also demonstrate two interesting insights: First, an adaptive scheduler able to find at runtime the right chunk size for each type of application and device configuration is an essential component for these kinds of heterogeneous platforms, and second, device configurations that provide higher throughput do not always achieve better energy eciency when only the running power (excluding the idle power component) is considered.
000089637 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T48$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-80920-R
000089637 540__ $$9info:eu-repo/semantics/openAccess$$aby-nc-nd$$uhttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
000089637 590__ $$a2.552$$b2019
000089637 591__ $$aCOMPUTER SCIENCE, SOFTWARE ENGINEERING$$b30 / 108 = 0.278$$c2019$$dQ2$$eT1
000089637 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b23 / 53 = 0.434$$c2019$$dQ2$$eT2
000089637 592__ $$a0.425$$b2019
000089637 593__ $$aSoftware$$c2019$$dQ2
000089637 593__ $$aHardware and Architecture$$c2019$$dQ2
000089637 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/submittedVersion
000089637 700__ $$aNavarro, Ángeles
000089637 700__ $$aAsenjo, Rafael
000089637 700__ $$aCorbera, Francisco
000089637 700__ $$0(orcid)0000-0002-4031-5651$$aGran, Rubén$$uUniversidad de Zaragoza
000089637 700__ $$0(orcid)0000-0002-7490-4067$$aSuárez, Darío$$uUniversidad de Zaragoza
000089637 700__ $$aNunez-Yanez, José
000089637 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000089637 773__ $$g98 (2019), 27-40$$pJ. systems archit.$$tJournal of Systems Architecture$$x1383-7621
000089637 8564_ $$s1015998$$uhttps://zaguan.unizar.es/record/89637/files/texto_completo.pdf$$yPreprint
000089637 8564_ $$s2399175$$uhttps://zaguan.unizar.es/record/89637/files/texto_completo.jpg?subformat=icon$$xicon$$yPreprint
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000089637 951__ $$a2021-03-03-16:11:44
000089637 980__ $$aARTICLE