89637 20210303162449.0 doi 10.1016/j.sysarc.2019.06.006 sideral 113301 ART-2019-113301 eng Rodríguez, Andrés Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs 2019 Access copy available to the general public Unrestricted This paper presents a framework targeted to low-cost and low-power heterogeneous MultiProcessors that exploits FPGAs and multicore CPUs, with the overarching goal of providing developers with a productive programming model and runtime support to fully use all the processing resources available. FPGA productivity is achieved using a high-level programming model based on OpenCL, the standard for cross-platform parallel heterogeneous programming. In this work, we focus on the parallel for pattern, and as part of the runtime support for this pattern, we leverage a new scheduler that strives to maximize the number of iterations per joule by dynamically and adaptively partitioning the iteration space between the multicore and the accelerator when working simultaneously. A total of 7 benchmarks are ported and optimized for a low-cost DE1 board. The results show that the heterogeneous solution can improve performance up to 2.9x and increases energy efficiency up to 2.7x compared tothe traditional approach of keeping all the CPU cores idle while the accelerator computes the workload. Our results also demonstrate two interesting insights: First, an adaptive scheduler able to find at runtime the right chunk size for each type of application and device configuration is an essential component for these kinds of heterogeneous platforms, and second, device configurations that provide higher throughput do not always achieve better energy eciency when only the running power (excluding the idle power component) is considered. info:eu-repo/grantAgreement/ES/DGA/T48 info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R info:eu-repo/grantAgreement/ES/MINECO/TIN2016-80920-R info:eu-repo/semantics/openAccess by-nc-nd http://creativecommons.org/licenses/by-nc-nd/3.0/es/ 2.552 2019 COMPUTER SCIENCE, SOFTWARE ENGINEERING 30 / 108 = 0.278 2019 Q2 T1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 23 / 53 = 0.434 2019 Q2 T2 0.425 2019 Software 2019 Q2 Hardware and Architecture 2019 Q2 info:eu-repo/semantics/article info:eu-repo/semantics/submittedVersion Navarro, Ángeles Asenjo, Rafael Corbera, Francisco (orcid)0000-0002-4031-5651 Gran, Rubén Universidad de Zaragoza (orcid)0000-0002-7490-4067 Suárez, Darío Universidad de Zaragoza Nunez-Yanez, José 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 98 (2019), 27-40 J. systems archit. Journal of Systems Architecture 1383-7621 1015998 http://zaguan.unizar.es/record/89637/files/texto_completo.pdf Preprint 2399175 http://zaguan.unizar.es/record/89637/files/texto_completo.jpg?subformat=icon icon Preprint oai:zaguan.unizar.es:89637 articulos driver 2021-03-03-16:11:44 ARTICLE