000094551 001__ 94551
000094551 005__ 20210902121753.0
000094551 0247_ $$2doi$$a10.1109/ACCESS.2020.2999062
000094551 0248_ $$2sideral$$a118596
000094551 037__ $$aART-2020-118596
000094551 041__ $$aeng
000094551 100__ $$aAnzola, Jon
000094551 245__ $$aReview of architectures based on partial power processing for DC-DC applications
000094551 260__ $$c2020
000094551 5060_ $$aAccess copy available to the general public$$fUnrestricted
000094551 5203_ $$aThis paper presents a review of advanced architectures based on the partial power processing concept, whose main objective is to achieve a reduction of the power processed by the converter. If the power processed by the converter is decreased, the power losses generated by the power converter are reduced, obtaining lower sized converters and higher system efficiencies. Through the review 3 different partial power processing strategies are distinguished: Differential Power Converters, Partial Power Converters and Mixed strategies. Each strategy is subdivided into smaller groups that entail different architectures with their own advantages and disadvantages. Also, due to the lack of agreement that exists in the sources around the naming of the different architectures, this paper seeks to stablish a nomenclature that avoids confusion when indexing this type of architectures. Regarding Partial Power Converters an extensive application oriented description is also developed. Finally, the main conclusions obtained through the review are presented.
000094551 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000094551 590__ $$a3.367$$b2020
000094551 591__ $$aCOMPUTER SCIENCE, INFORMATION SYSTEMS$$b65 / 162 = 0.401$$c2020$$dQ2$$eT2
000094551 591__ $$aTELECOMMUNICATIONS$$b36 / 91 = 0.396$$c2020$$dQ2$$eT2
000094551 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b94 / 273 = 0.344$$c2020$$dQ2$$eT2
000094551 592__ $$a0.586$$b2020
000094551 593__ $$aComputer Science (miscellaneous)$$c2020$$dQ1
000094551 593__ $$aMaterials Science (miscellaneous)$$c2020$$dQ1
000094551 593__ $$aEngineering (miscellaneous)$$c2020$$dQ1
000094551 655_4 $$ainfo:eu-repo/semantics/review$$vinfo:eu-repo/semantics/publishedVersion
000094551 700__ $$aAizpuru, Iosu
000094551 700__ $$aArruti Romero, Asier
000094551 700__ $$aAlacano Loiti, Argiñe
000094551 700__ $$aLópez-Erauskin, Ramón
000094551 700__ $$0(orcid)0000-0001-7764-235X$$aArtal-Sevil, Jesús S.$$uUniversidad de Zaragoza
000094551 700__ $$0(orcid)0000-0001-9334-4870$$aBernal, Carlos$$uUniversidad de Zaragoza
000094551 7102_ $$15008$$2785$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Tecnología Electrónica
000094551 7102_ $$15009$$2535$$aUniversidad de Zaragoza$$bDpto. Ingeniería Eléctrica$$cÁrea Ingeniería Eléctrica
000094551 773__ $$g8 (2020), 103405-103418$$pIEEE Access$$tIEEE Access$$x2169-3536
000094551 8564_ $$s7382945$$uhttps://zaguan.unizar.es/record/94551/files/texto_completo.pdf$$yVersión publicada
000094551 8564_ $$s558812$$uhttps://zaguan.unizar.es/record/94551/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000094551 909CO $$ooai:zaguan.unizar.es:94551$$particulos$$pdriver
000094551 951__ $$a2021-09-02-09:50:26
000094551 980__ $$aARTICLE