DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

Valero, A. (Universidad de Zaragoza) ; Suarez-Gracia, D. (Universidad de Zaragoza) ; Gran-Tejero, R. (Universidad de Zaragoza)

Resumen: The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.

Idioma: Inglés

DOI: 10.1109/ACCESS.2020.3025899

Año: 2020

Publicado en: IEEE Access 8 (2020), 173276-173288
ISSN: 2169-3536

Factor impacto JCR: 3.367 (2020)

Categ. JCR: COMPUTER SCIENCE, INFORMATION SYSTEMS rank: 65 / 162 = 0.401 (2020) - Q2 - T2
Categ. JCR: TELECOMMUNICATIONS rank: 36 / 91 = 0.396 (2020) - Q2 - T2
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 94 / 273 = 0.344 (2020) - Q2 - T2

Factor impacto SCIMAGO: 0.586 - Computer Science (miscellaneous) (Q1) - Materials Science (miscellaneous) (Q1) - Engineering (miscellaneous) (Q1)

Financiación: info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R
Financiación: info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón
Financiación: info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/CICYT-PID2019-105660RB-C21
Financiación: info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2016-76635-C2-1-R
Financiación: info:eu-repo/grantAgreement/ES/UZ/JIUZ-2019-TEC-08

Tipo y forma: Artículo (Versión definitiva)

Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)