000097243 001__ 97243
000097243 005__ 20210902121845.0
000097243 0247_ $$2doi$$a10.1109/ACCESS.2020.3032145
000097243 0248_ $$2sideral$$a120945
000097243 037__ $$aART-2020-120945
000097243 041__ $$aeng
000097243 100__ $$0(orcid)0000-0003-1550-735X$$aSegarra, J.$$uUniversidad de Zaragoza
000097243 245__ $$aAutomatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches
000097243 260__ $$c2020
000097243 5060_ $$aAccess copy available to the general public$$fUnrestricted
000097243 5203_ $$aWorst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this article, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%.
000097243 536__ $$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2016-76635-C2-1-R$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2017-86727-C2-1-R
000097243 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000097243 590__ $$a3.367$$b2020
000097243 591__ $$aCOMPUTER SCIENCE, INFORMATION SYSTEMS$$b65 / 162 = 0.401$$c2020$$dQ2$$eT2
000097243 591__ $$aTELECOMMUNICATIONS$$b36 / 91 = 0.396$$c2020$$dQ2$$eT2
000097243 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b94 / 273 = 0.344$$c2020$$dQ2$$eT2
000097243 592__ $$a0.586$$b2020
000097243 593__ $$aComputer Science (miscellaneous)$$c2020$$dQ1
000097243 593__ $$aMaterials Science (miscellaneous)$$c2020$$dQ1
000097243 593__ $$aEngineering (miscellaneous)$$c2020$$dQ1
000097243 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000097243 700__ $$aCortadella, J.
000097243 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, R.$$uUniversidad de Zaragoza
000097243 700__ $$0(orcid)0000-0002-5976-1352$$aViñals-Yufera, V.$$uUniversidad de Zaragoza
000097243 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000097243 773__ $$g8 (2020), 192379-192392$$pIEEE Access$$tIEEE Access$$x2169-3536
000097243 8564_ $$s1457122$$uhttps://zaguan.unizar.es/record/97243/files/texto_completo.pdf$$yVersión publicada
000097243 8564_ $$s580168$$uhttps://zaguan.unizar.es/record/97243/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000097243 909CO $$ooai:zaguan.unizar.es:97243$$particulos$$pdriver
000097243 951__ $$a2021-09-02-10:26:16
000097243 980__ $$aARTICLE