97243 20210902121845.0 doi 10.1109/ACCESS.2020.3032145 sideral 120945 ART-2020-120945 eng Segarra, J. Universidad de Zaragoza (orcid)0000-0003-1550-735X Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches 2020 Access copy available to the general public Unrestricted Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this article, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%. info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21 info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2016-76635-C2-1-R info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2017-86727-C2-1-R info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 3.367 2020 COMPUTER SCIENCE, INFORMATION SYSTEMS 65 / 162 = 0.401 2020 Q2 T2 TELECOMMUNICATIONS 36 / 91 = 0.396 2020 Q2 T2 ENGINEERING, ELECTRICAL & ELECTRONIC 94 / 273 = 0.344 2020 Q2 T2 0.586 2020 Computer Science (miscellaneous) 2020 Q1 Materials Science (miscellaneous) 2020 Q1 Engineering (miscellaneous) 2020 Q1 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Cortadella, J. Gran Tejero, R. Universidad de Zaragoza (orcid)0000-0002-4031-5651 Viñals-Yufera, V. Universidad de Zaragoza (orcid)0000-0002-5976-1352 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 8 (2020), 192379-192392 IEEE Access IEEE Access 2169-3536 1457122 http://zaguan.unizar.es/record/97243/files/texto_completo.pdf Versión publicada 580168 http://zaguan.unizar.es/record/97243/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:97243 articulos driver 2021-09-02-10:26:16 ARTICLE