000112116 001__ 112116 000112116 005__ 20240319080957.0 000112116 0247_ $$2doi$$a10.1016/j.sysarc.2021.102372 000112116 0248_ $$2sideral$$a128086 000112116 037__ $$aART-2022-128086 000112116 041__ $$aeng 000112116 100__ $$0(orcid)0000-0003-0668-6229$$aDavila-Guzman, M. A.$$uUniversidad de Zaragoza 000112116 245__ $$aA cross-platform OpenVX library for FPGA accelerators 000112116 260__ $$c2022 000112116 5060_ $$aAccess copy available to the general public$$fUnrestricted 000112116 5203_ $$aFPGAs are an excellent platform to implement computer vision applications, since these applications tend to offer a high level of parallelism with many data-independent operations. However, the freedom in the solution design space of FPGAs represents a problem because each solution must be individually designed, verified, and tuned. The emergence of High Level Synthesis (HLS) helps solving this problem and has allowed the implementation of open programming standards as OpenVX for computer vision applications on FPGAs, such as the HiF1ipVX library developed exclusively for Xilinx devices. Although with the HiF1ipVX library, designers can develop solutions efficiently on Xilinx, they do not have an approach to port and run their code on FPGAs from other manufacturers. This work extends the HiFlipVX capabilities in two significant ways: supporting Intel FPGA devices and enabling execution on discrete FPGA accelerators. To provide both without affecting user-facing code, the new carried out implementation combines two HLS programming models: C++, using Intel''s system of tasks, and OpenCL, which provides the CPU interoperability. Comparing with pure OpenCL implementations, this work reduces kernel dispatch resources, saving up to 24% of ALUT resources for each kernel in a graph, and improves performance 2.6 x and energy consumption 1.6 x on average for a set of representative applications, compared with state-of-the-art frameworks. 000112116 536__ $$9info:eu-repo/grantAgreement/ES/AEI-FEDER/PID2019-105660RB-C21$$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R 000112116 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/ 000112116 590__ $$a4.5$$b2022 000112116 592__ $$a1.276$$b2022 000112116 591__ $$aCOMPUTER SCIENCE, SOFTWARE ENGINEERING$$b22 / 108 = 0.204$$c2022$$dQ1$$eT1 000112116 593__ $$aSoftware$$c2022$$dQ1 000112116 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b11 / 54 = 0.204$$c2022$$dQ1$$eT1 000112116 593__ $$aHardware and Architecture$$c2022$$dQ1 000112116 594__ $$a8.5$$b2022 000112116 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion 000112116 700__ $$aKalms, L. 000112116 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, R.$$uUniversidad de Zaragoza 000112116 700__ $$0(orcid)0000-0003-3000-0506$$aVillarroya-Gaudo, M.$$uUniversidad de Zaragoza 000112116 700__ $$0(orcid)0000-0002-7490-4067$$aSuarez Gracia, D.$$uUniversidad de Zaragoza 000112116 700__ $$aGöhringer, D. 000112116 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000112116 773__ $$g123 (2022), 102372 [10 pp.]$$pJ. systems archit.$$tJournal of Systems Architecture$$x1383-7621 000112116 8564_ $$s1602462$$uhttps://zaguan.unizar.es/record/112116/files/texto_completo.pdf$$yVersión publicada 000112116 8564_ $$s2623116$$uhttps://zaguan.unizar.es/record/112116/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada 000112116 909CO $$ooai:zaguan.unizar.es:112116$$particulos$$pdriver 000112116 951__ $$a2024-03-18-13:46:44 000112116 980__ $$aARTICLE