000125237 001__ 125237
000125237 005__ 20241125101133.0
000125237 0247_ $$2doi$$a10.1371/journal.pone.0278346
000125237 0248_ $$2sideral$$a133019
000125237 037__ $$aART-2023-133019
000125237 041__ $$aeng
000125237 100__ $$aEscuin, Carlos$$uUniversidad de Zaragoza
000125237 245__ $$aL2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime
000125237 260__ $$c2023
000125237 5060_ $$aAccess copy available to the general public$$fUnrestricted
000125237 5203_ $$aSeveral emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.
000125237 536__ $$9info:eu-repo/grantAgreement/ES/AEI-FEDER/PID2019-105660RB-C21$$9info:eu-repo/grantAgreement/ES/AEI/PID2019-103939RB-I00$$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/MICINN-AEI/PDC2021-120898-I00
000125237 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000125237 590__ $$a2.9$$b2023
000125237 592__ $$a0.839$$b2023
000125237 591__ $$aMULTIDISCIPLINARY SCIENCES$$b32 / 134 = 0.239$$c2023$$dQ1$$eT1
000125237 593__ $$aMultidisciplinary$$c2023$$dQ1
000125237 594__ $$a6.2$$b2023
000125237 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000125237 700__ $$0(orcid)0000-0002-5916-7898$$aIbáñez, Pablo$$uUniversidad de Zaragoza
000125237 700__ $$0(orcid)0000-0002-0795-8743$$aNavarro, Denis$$uUniversidad de Zaragoza
000125237 700__ $$aMonreal, Teresa
000125237 700__ $$aLlabería, José M.
000125237 700__ $$0(orcid)0000-0002-5976-1352$$aViñals, Víctor$$uUniversidad de Zaragoza
000125237 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000125237 7102_ $$15008$$2785$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Tecnología Electrónica
000125237 773__ $$g18, 2 (2023), e0278346 [36 pp.]$$pPLoS One$$tPLoS ONE$$x1932-6203
000125237 8564_ $$s2861763$$uhttps://zaguan.unizar.es/record/125237/files/texto_completo.pdf$$yVersión publicada
000125237 8564_ $$s2539241$$uhttps://zaguan.unizar.es/record/125237/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000125237 909CO $$ooai:zaguan.unizar.es:125237$$particulos$$pdriver
000125237 951__ $$a2024-11-22-11:59:48
000125237 980__ $$aARTICLE