Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Serrano-Reyes, Andrés ; Sanz-Pascual, María Teresa ; Calvo-López, Belén (Universidad de Zaragoza)

Resumen: Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

Idioma: Inglés

DOI: 10.3390/electronics12224638

Año: 2023

Publicado en: Electronics 12, 22 (2023), 4638 [13 pp.]
ISSN: 2079-9292

Factor impacto JCR: 2.6 (2023)

Categ. JCR: COMPUTER SCIENCE, INFORMATION SYSTEMS rank: 115 / 250 = 0.46 (2023) - Q2 - T2
Categ. JCR: PHYSICS, APPLIED rank: 81 / 179 = 0.453 (2023) - Q2 - T2
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 157 / 353 = 0.445 (2023) - Q2 - T2

Factor impacto CITESCORE: 5.3 - Hardware and Architecture (Q2) - Control and Systems Engineering (Q2) - Electrical and Electronic Engineering (Q2) - Signal Processing (Q2) - Computer Networks and Communications (Q2)

Factor impacto SCIMAGO: 0.644 - Electrical and Electronic Engineering (Q2) - Computer Networks and Communications (Q2) - Signal Processing (Q2) - Hardware and Architecture (Q2) - Control and Systems Engineering (Q2)

Financiación: info:eu-repo/grantAgreement/ES/MCIU/PID2019-106570RB-I00-AEI-10.13039-501100011033

Tipo y forma: Article (Published version)

Área (Departamento): Área Electrónica (Dpto. Ingeniería Electrón.Com.)