000131704 001__ 131704
000131704 005__ 20250923084414.0
000131704 0247_ $$2doi$$a10.1016/j.micpro.2024.105023
000131704 0248_ $$2sideral$$a136807
000131704 037__ $$aART-2024-136807
000131704 041__ $$aeng
000131704 100__ $$aToca-Díaz, Yamilka$$uUniversidad de Zaragoza
000131704 245__ $$aFlip-and-Patch: A Fault-Tolerant Technique for On-Chip Memories of CNN Accelerators at Low Supply Voltage
000131704 260__ $$c2024
000131704 5060_ $$aAccess copy available to the general public$$fUnrestricted
000131704 5203_ $$aAggressively reducing the supply voltage () below the safe threshold voltage () can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes.
This work addresses the impact of permanent faults on the accuracy of a Convolutional Neural Network (CNN) inference accelerator using on-chip activation memories supplied at low below Based on a characterization study of fault patterns, this paper proposes two low-cost microarchitectural techniques, namely Flip-and-Patch, which maintain the original accuracy of CNN applications even in the presence of a high number of faults caused by operating at. Unlike existing techniques, Flip-and-Patch remains transparent to the programmer and does not rely on application characteristics, making it easily applicable to real CNN accelerators.
Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%.
000131704 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58-23R$$9info:eu-repo/grantAgreement/ES/AEI-FEDER/PID2019-105660RB-C21
000131704 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000131704 590__ $$a2.6$$b2024
000131704 592__ $$a0.493$$b2024
000131704 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b30 / 60 = 0.5$$c2024$$dQ2$$eT2
000131704 593__ $$aComputer Networks and Communications$$c2024$$dQ2
000131704 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b172 / 366 = 0.47$$c2024$$dQ2$$eT2
000131704 593__ $$aSoftware$$c2024$$dQ2
000131704 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b54 / 147 = 0.367$$c2024$$dQ2$$eT2
000131704 593__ $$aHardware and Architecture$$c2024$$dQ2
000131704 593__ $$aArtificial Intelligence$$c2024$$dQ3
000131704 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000131704 700__ $$aHernández Palacios, Reynier
000131704 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, Rubén$$uUniversidad de Zaragoza
000131704 700__ $$0(orcid)0000-0002-0824-5833$$aValero, Alejandro$$uUniversidad de Zaragoza
000131704 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000131704 773__ $$g106 (2024), 105023 [13 pp.]$$pMicroprocess. microsyst.$$tMICROPROCESSORS AND MICROSYSTEMS$$x0141-9331
000131704 8564_ $$s1334433$$uhttps://zaguan.unizar.es/record/131704/files/texto_completo.pdf$$yVersión publicada
000131704 8564_ $$s2572433$$uhttps://zaguan.unizar.es/record/131704/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000131704 909CO $$ooai:zaguan.unizar.es:131704$$particulos$$pdriver
000131704 951__ $$a2025-09-22-14:31:45
000131704 980__ $$aARTICLE