Flip-and-Patch: A Fault-Tolerant Technique for On-Chip Memories of CNN Accelerators at Low Supply Voltage

Toca-Díaz, Yamilka (Universidad de Zaragoza) ; Hernández Palacios, Reynier ; Gran Tejero, Rubén (Universidad de Zaragoza) ; Valero, Alejandro (Universidad de Zaragoza)

Resumen: Aggressively reducing the supply voltage () below the safe threshold voltage () can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes.

This work addresses the impact of permanent faults on the accuracy of a Convolutional Neural Network (CNN) inference accelerator using on-chip activation memories supplied at low below Based on a characterization study of fault patterns, this paper proposes two low-cost microarchitectural techniques, namely Flip-and-Patch, which maintain the original accuracy of CNN applications even in the presence of a high number of faults caused by operating at. Unlike existing techniques, Flip-and-Patch remains transparent to the programmer and does not rely on application characteristics, making it easily applicable to real CNN accelerators.

Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%.

Idioma: Inglés

DOI: 10.1016/j.micpro.2024.105023

Año: 2024

Publicado en: MICROPROCESSORS AND MICROSYSTEMS 106 (2024), 105023 [13 pp.]
ISSN: 0141-9331

Factor impacto JCR: 2.6 (2024)

Categ. JCR: COMPUTER SCIENCE, HARDWARE & ARCHITECTURE rank: 30 / 60 = 0.5 (2024) - Q2 - T2
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 172 / 366 = 0.47 (2024) - Q2 - T2
Categ. JCR: COMPUTER SCIENCE, THEORY & METHODS rank: 54 / 147 = 0.367 (2024) - Q2 - T2

Factor impacto SCIMAGO: 0.493 - Computer Networks and Communications (Q2) - Software (Q2) - Hardware and Architecture (Q2) - Artificial Intelligence (Q3)

Financiación: info:eu-repo/grantAgreement/ES/AEI-FEDER/PID2019-105660RB-C21
Financiación: info:eu-repo/grantAgreement/ES/DGA/T58-23R

Tipo y forma: Artículo (Versión definitiva)

Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)