Resumen: Applications of Binary Neural Networks (BNNs) are promising for embedded systems with hard constraints on energy and computing power. Contrary to conventional neural networks using floating-point datatypes, BNNs use binarized weights and activations to reduce memory and computation requirements. Memristors, emerging non-volatile memory devices, show great potential as a target implementation platform for BNNs by integrating storage and compute units. However, the efficiency of this hardware highly depends on how the network is mapped and executed on these devices. In this paper, we propose an efficient implementation of XNOR-based BNN to maximize parallelization. In this implementation, costly analog-to-digital converters are replaced with sense amplifiers with custom reference(s) to generate activation values. Besides, a novel mapping is introduced to minimize the overhead of data communication between convolution layers mapped to different memristor crossbars. This comes with extensive analytical and simulation-based analysis to evaluate the implication of different design choices considering the accuracy of the network. The results show that our approach achieves up to 5 × energy-saving and 100 × improvement in latency compared to baselines. Idioma: Inglés DOI: 10.1109/TETC.2024.3406628 Año: 2024 Publicado en: IEEE Transactions on Emerging Topics in Computing 13, 2 (2024), 395 - 408 ISSN: 2168-6750 Factor impacto JCR: 5.4 (2024) Categ. JCR: TELECOMMUNICATIONS rank: 28 / 120 = 0.233 (2024) - Q1 - T1 Categ. JCR: COMPUTER SCIENCE, INFORMATION SYSTEMS rank: 42 / 258 = 0.163 (2024) - Q1 - T1 Factor impacto SCIMAGO: 1.284 - Computer Science (miscellaneous) (Q1) - Information Systems (Q1) - Human-Computer Interaction (Q1) - Computer Science Applications (Q1)
Tipo y forma: Article (PostPrint)
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