Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs
Resumen: Networks on Chip (NoCs) have a large impact on system performance, area, and energy. NoCs convey request and response messages among cores following the message patterns dictated by the cache banks. Such patterns do not only guarantee a coherent memory state, but also provide an opportunity for NoC optimization. Request messages can smartly reserve the resources to dynamically build a circuit for replies, thus reducing their network latency. Starting from this simple idea, which we denote Reactive Circuits, we evaluate several implementations of the mechanism: with and without sharing circuits between messages, performing timed reservations, and removing the implicit coherence messages. A careful implementation of this circuit reservation mechanism in a wormhole router achieves an average 20.8% reduction in network energy consumption, 5.8% smaller router area and a 4.8% system performance increase in a 64-core chip, compared with a conventional network.
Idioma: Inglés
DOI: 10.1016/j.jpdc.2016.04.002
Año: 2016
Publicado en: Journal of Parallel and Distributed Computing 95 (2016), 57-68
ISSN: 0743-7315

Factor impacto JCR: 1.93 (2016)
Categ. JCR: COMPUTER SCIENCE, THEORY & METHODS rank: 34 / 104 = 0.327 (2016) - Q2 - T1
Factor impacto SCIMAGO: 0.596 - Hardware and Architecture (Q1) - Computer Networks and Communications (Q1) - Theoretical Computer Science (Q2) - Software (Q2) - Artificial Intelligence (Q2)

Financiación: info:eu-repo/grantAgreement/ES/DGA/T48
Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P
Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC
Tipo y forma: Article (PrePrint)
Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)
Exportado de SIDERAL (2022-01-20-22:54:01)


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articulos > articulos-por-area > arquitectura_y_tecnologia_de_computadores



 Notice créée le 2016-10-19, modifiée le 2022-01-20


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