000096218 001__ 96218
000096218 005__ 20230313141237.0
000096218 0247_ $$2doi$$a10.1109/ACCESS.2020.3025899
000096218 0248_ $$2sideral$$a120531
000096218 037__ $$aART-2020-120531
000096218 041__ $$aeng
000096218 100__ $$0(orcid)0000-0002-0824-5833$$aValero, A.$$uUniversidad de Zaragoza
000096218 245__ $$aDC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files
000096218 260__ $$c2020
000096218 5060_ $$aAccess copy available to the general public$$fUnrestricted
000096218 5203_ $$aThe ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.
000096218 536__ $$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/CICYT-PID2019-105660RB-C21$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2016-76635-C2-1-R$$9info:eu-repo/grantAgreement/ES/UZ/JIUZ-2019-TEC-08
000096218 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000096218 590__ $$a3.367$$b2020
000096218 591__ $$aCOMPUTER SCIENCE, INFORMATION SYSTEMS$$b65 / 162 = 0.401$$c2020$$dQ2$$eT2
000096218 591__ $$aTELECOMMUNICATIONS$$b36 / 91 = 0.396$$c2020$$dQ2$$eT2
000096218 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b94 / 273 = 0.344$$c2020$$dQ2$$eT2
000096218 592__ $$a0.586$$b2020
000096218 593__ $$aComputer Science (miscellaneous)$$c2020$$dQ1
000096218 593__ $$aMaterials Science (miscellaneous)$$c2020$$dQ1
000096218 593__ $$aEngineering (miscellaneous)$$c2020$$dQ1
000096218 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000096218 700__ $$0(orcid)0000-0002-7490-4067$$aSuarez-Gracia, D.$$uUniversidad de Zaragoza
000096218 700__ $$0(orcid)0000-0002-4031-5651$$aGran-Tejero, R.$$uUniversidad de Zaragoza
000096218 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000096218 773__ $$g8 (2020), 173276-173288$$pIEEE Access$$tIEEE Access$$x2169-3536
000096218 8564_ $$s967472$$uhttps://zaguan.unizar.es/record/96218/files/texto_completo.pdf$$yVersión publicada
000096218 8564_ $$s543891$$uhttps://zaguan.unizar.es/record/96218/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000096218 909CO $$ooai:zaguan.unizar.es:96218$$particulos$$pdriver
000096218 951__ $$a2023-03-13-13:55:46
000096218 980__ $$aARTICLE