Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

Segarra, J. (Universidad de Zaragoza) ; Cortadella, J. ; Gran Tejero, R. (Universidad de Zaragoza) ; Viñals-Yufera, V. (Universidad de Zaragoza)

Resumen: Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this article, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%.

Idioma: Inglés

DOI: 10.1109/ACCESS.2020.3032145

Año: 2020

Publicado en: IEEE Access 8 (2020), 192379-192392
ISSN: 2169-3536

Factor impacto JCR: 3.367 (2020)

Categ. JCR: COMPUTER SCIENCE, INFORMATION SYSTEMS rank: 65 / 162 = 0.401 (2020) - Q2 - T2
Categ. JCR: TELECOMMUNICATIONS rank: 36 / 91 = 0.396 (2020) - Q2 - T2
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 94 / 273 = 0.344 (2020) - Q2 - T2

Factor impacto SCIMAGO: 0.586 - Computer Science (miscellaneous) (Q1) - Materials Science (miscellaneous) (Q1) - Engineering (miscellaneous) (Q1)

Financiación: info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R
Financiación: info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón
Financiación: info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21
Financiación: info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2016-76635-C2-1-R
Financiación: info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2017-86727-C2-1-R

Tipo y forma: Article (Published version)

Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)