Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA

Olivito, Javier (Universidad de Zaragoza) ; Serrano, Felipe ; Clemente, Juan Antonio ; Mecha, Hortensia ; Resano, Javier (Universidad de Zaragoza)

Resumen: In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.

Idioma: Inglés

DOI: 10.1049/iet-cdt.2016.0095

Año: 2018

Publicado en: IET Computers and Digital Techniques 12, 4 (2018), [33 pp]
ISSN: 1751-8601

Factor impacto JCR: 0.857 (2018)

Categ. JCR: COMPUTER SCIENCE, THEORY & METHODS rank: 75 / 104 = 0.721 (2018) - Q3 - T3
Categ. JCR: COMPUTER SCIENCE, HARDWARE & ARCHITECTURE rank: 46 / 52 = 0.885 (2018) - Q4 - T3

Factor impacto SCIMAGO: 0.19 - Electrical and Electronic Engineering (Q3) - Software (Q3) - Hardware and Architecture (Q3)

Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P
Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC

Tipo y forma: Artículo (PrePrint)

Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)