Behavioral model for high-speed SAR ADCs with on-chip references

Dominguez-Matas, Carlos ; Gines, Antonio ; Otin, Aranzazu (Universidad de Zaragoza) ; Gutiérrez, Valentín ; Leger, Gildas ; Peralias, Eduardo

Resumen: This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming LC package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level.

Idioma: Inglés

DOI: 10.1109/TVLSI.2023.3314067

Año: 2023

Publicado en: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 31, 12 (2023), 1918-1930
ISSN: 1063-8210

Factor impacto JCR: 2.8 (2023)

Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 151 / 353 = 0.428 (2023) - Q2 - T2
Categ. JCR: COMPUTER SCIENCE, HARDWARE & ARCHITECTURE rank: 23 / 59 = 0.39 (2023) - Q2 - T2

Factor impacto CITESCORE: 6.4 - Electrical and Electronic Engineering (Q1) - Hardware and Architecture (Q2) - Software (Q2)

Factor impacto SCIMAGO: 0.937 - Electrical and Electronic Engineering (Q1) - Software (Q2) - Hardware and Architecture (Q2)

Financiación: info:eu-repo/grantAgreement/ES/AEI/RTI2018-098513-B-I00

Tipo y forma: Artículo (PostPrint)

Área (Departamento): Área Tecnología Electrónica (Dpto. Ingeniería Electrón.Com.)