High-Linearity Self-Biased CMOS Current Buffer
Resumen: A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.
Idioma: Inglés
DOI: 10.3390/electronics7120423
Año: 2018
Publicado en: ELECTRONICS 7, 12 (2018), 423 [18 pp]
ISSN: 2079-9292

Factor impacto JCR: 1.764 (2018)
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 154 / 265 = 0.581 (2018) - Q3 - T2
Factor impacto SCIMAGO: 0.461 - Computer Networks and Communications (Q1) - Control and Systems Engineering (Q1) - Signal Processing (Q1) - Hardware and Architecture (Q1) - Electrical and Electronic Engineering (Q1)

Financiación: info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2015-65750-R
Tipo y forma: Article (Published version)
Área (Departamento): Área Electrónica (Dpto. Ingeniería Electrón.Com.)

Creative Commons You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.


Exportado de SIDERAL (2020-01-17-21:57:48)

Este artículo se encuentra en las siguientes colecciones:
Articles



 Record created 2019-02-19, last modified 2020-01-17


Versión publicada:
 PDF
Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)